Description: Note: Any images shown are stock photographs and product may differ from what is shown. You are purchasing a Very Good copy of 'Verification Methodology Manual for SystemVerilog'Condition Notes: Supports Goodwill of Silicon Valley job training programs. The cover and pages are in very good condition! The cover and any other included accessories are also in very good condition showing some minor use. The spine is straight, there are no rips tears or creases on the cover or the pages.
Price: 15.74 USD
Location: San Jose, California
End Time: 2024-11-18T16:51:23.000Z
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Return shipping will be paid by: Buyer
All returns accepted: Returns Accepted
Item must be returned within: 30 Days
Refund will be given as: Money Back
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Release Year: 2005
Book Title: Verification Methodology Manual for SystemVerilog
Number of Pages: Xvii, 503 Pages
Publication Name: Verification Methodology Manual for Systemverilog
Language: English
Publisher: Springer
Publication Year: 2005
Subject: Cad-Cam, General, Electronics / Circuits / General, Compilers
Item Weight: 70.5 Oz
Type: Textbook
Author: Andy Nightingale, Janick Bergeron, Alan Hunter, Eduard Cerny
Subject Area: Computers, Technology & Engineering
Item Length: 9.3 in
Item Width: 6.1 in
Format: Hardcover
